Vedic algorithm for cubic computation and VLSI implementation

چکیده مقاله :
Algorithm of cubic computation and its VLSI implementation is described in this paper through ‘Vedic
mathematics’ formulae. An N-bit cubic implementation circuit was structured into two cubic subgroups
(bit length = N2
or lesser), multiplier and adder. VLSI aspects such as propagation delay and dynamic power
consumption of such circuitry were lessened down notably by reducing the number of partial products.
Designs implementation and estimation of performance parameters: delay and power consumption were
figured out by spice spectre with 90 nm CMOS technology. The estimated values for propagation delay
and power consumption of the reported 8-bit cubic circuitry were 5.5 ns and 2.6mW respectively.
Propagation delay has been enhanced by 12% and power consumption dropped down by 22% in comparison
to its counterpart (traditional architecture).

توضیحات تکمیلی :

مقاله ISI انگلیسی اصلی
سال انتشار:2017
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نویسندگان/توضیحات : مقاله ISI سال انتشار2017 \ Deepak Kumar a,⇑, Prabir Saha b, Anup Dandapat
تاریخ ارسال : 1397/10/28
تعداد بازدید : 278
کلمات کلیدی : Anurupyena Cubic High speed Vedic mathematics Yavadunam sutra (YVDN)
تعداد صفحات : 6
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